H8SSLASH2214 datasheet(411/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 351 of 872

REJ09B0189-0400

After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin

states, as PFDDR and PFDR are initialized. PORTF retains its previous state after a manual reset

and in software standby mode.

9.12.3

Pin Functions

Port F pins also function as external interrupt input pins (

IRQ2 and IRQ3), bus control signal I/O

pins (

AS, RD, HWR, LWR, WAIT, BREQ, and BACK), and the system clock (φ) output pin. The

pin functions differ between modes 4 to 6 and mode 7. Port F pin functions are shown in table

9.23.

Table 9.23

Port F Pin Functions

Pin Functions and Selection Method

PF7/

The pin function is switched as shown below according to bit PF7DDR.

PF7DDR

Pin function

PF7 input

φ output

PF6/

The pin function is switched as shown below according to the operating mode and bit

PF6DDR.

Operating mode

Modes 4 to 6

Mode 7

PF6DDR

—

Pin function

AS output

PF6 input

PF6 output

PF5/

The pin function is switched as shown below according to the operating mode and bit

PF5DDR.

Operating mode

Modes 4 to 6

Mode 7

PF5DDR

—

Pin function

RD output

PF5 input

PF5 output

PF4/

HWR The pin function is switched as shown below according to the operating mode and bit

PF4DDR.

Operating mode

Modes 4 to 6

Mode 7

PF4DDR

—

Pin function

HWR output

PF4 input

PF4 output

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