H8SSLASH2214 datasheet(410/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 350 of 872

REJ09B0189-0400

(a) Modes 4 to 6

Pin PF7 functions as the

φ output pin when the corresponding PFDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

The input/output direction specification in PFDDR is ignored for pins PF6 to PF3, which are

automatically designated as bus control outputs (

AS, RD, HWR, and LWR).

Pins PF2 to PF0 are made bus control input/output pins (

WAIT, BACK, and BREQ) by bus

controller settings. Otherwise, setting a PFDDR bit to 1 makes the corresponding pin an output

port, while clearing the bit to 0 makes the pin an input port.

(b) Mode 7

Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in

the case of pin PF7, the

φ output pin. Clearing the bit to 0 makes the pin an input port.

(2) Port F Data Register (PFDR)

PF7DR

PF6DR

R/W

PF5DR

R/W

PF4DR

R/W

PF3DR

R/W

PF0DR

R/W

PF2DR

R/W

PF1DR

R/W

Bit

Initial value

R/W

PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF0).

PFDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its

previous state after a manual reset and in software standby mode.

(3) Port F Register (PORTF)

PF7

—*

PF6

—*

PF5

—*

PF4

—*

PF3

—*

PF0

—*

PF2

—*

PF1

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins PF7 to PF0.

PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port F pins (PF7 to PF0) must always be performed on PFDR.

If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F

read is performed while PFDDR bits are cleared to 0, the pin states are read.

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