H8SSLASH2214 datasheet(416/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 356 of 872

REJ09B0189-0400

If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G

read is performed while PGDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin

states, as PGDDR and PGDR are initialized. PORTG retains its previous state after a manual reset

and in software standby mode.

9.13.3

Pin Functions

Port G pins also function as external interrupt input pins (

IRQ6 and IRQ7) and bus control signal

output pins (

CS0 to CS3). The pin functions differ between modes 4 to 6 and mode 7. Port G pin

functions are shown in table 9.25.

Table 9.25

Port G Pin Functions

Pin Functions and Selection Method

PG4/

CS0

The pin function is switched as shown below according to the operating mode and bit

PG4DDR.

Operating mode

Modes 4 to 6

Mode 7

PG4DDR

Pin function

PG4 input

CS0 output

PG4 input

PG4 output

PG3/

CS1

The pin function is switched as shown below according to the operating mode and bit

PG3DDR.

Operating mode

Modes 4 to 6

Mode 7

PG3DDR

Pin function

PG3 input

CS1 output

PG3 input

PG3 output

PG2/

CS2

The pin function is switched as shown below according to the operating mode and bit

PG2DDR.

Operating mode

Modes 4 to 6

Mode 7

PG2DDR

Pin function

PG2 input

CS2 output

PG2 input

PG2 output

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