H8SSLASH2214 datasheet(414/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 354 of 872

REJ09B0189-0400

9.13.2

Table 9.24 shows the port G register configuration.

Table 9.24

Port G Registers

Name

Abbreviation

R/W

Initial Value*

Address*

Port G data direction register

PGDDR

H'10/H'00*

H'FE3F

Port G data register

PGDR

R/W

H'00

H'FF0F

Port G register

PORTG

Undefined

H'FFBF

Notes: 1. Lower 16 bits of the address.

2. Value of bits 4 to 0.

3. Initial value depends on the mode. Initialized to H'10 in modes 4 and 5, and to H'00 in

modes 6 and 7.

(1) Port G Data Direction Register (PGDDR)

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

PG4DDR

PG3DDR

PG0DDR

PG2DDR

PG1DDR

Bit

Modes 4 and 5 :

Initial value

R/W

Modes 6 and 7 :

Initial value

R/W

PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port G. PGDDR cannot be read. Also, bits 7 to 5 are reserved, and will return an undefined

value if read.

Setting a PGDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit

to 0, makes the pin an input pin. Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section 2.10.4, Access Methods for

Registers with Write-Only Bits.

Bit PG4DDR is initialized to 1 (modes 4 and 5) or 0 (modes 6 and 7) by a power-on reset and in

hardware standby mode. PGDDR retains its previous state after a manual reset and in software

standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain

their output state or become high-impedance when a transition is made to software standby mode.

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