H8SSLASH2214 datasheet(415/936 Pages) RENESAS

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Section 9 I/O Ports

Rev.4.00 Sep. 18, 2008 Page 355 of 872

REJ09B0189-0400

(a) Modes 4 to 6

Pins PG4 to PG1 function as bus control signal output pins (

CS0 to CS3) when the

corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.

Pin PG0 functions as an output port when the corresponding PGDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

(b) Mode 7

Setting a PGDDR bit to 1 makes the corresponding pin an output port, while clearing the bit to

0 makes the pin an input port.

(2) Port G Data Register (PGDR)

—

Undefined

—

Undefined

—

Undefined

—

PG4DR

R/W

PG3DR

R/W

PG0DR

R/W

PG2DR

R/W

PG1DR

R/W

Bit

Initial value :

R/W

PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to

PG0).

Bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read.

PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset and in hardware standby mode. It

retains its previous state after a manual reset and in software standby mode.

(3) Port G Register (PORTG)

—

Undefined

—

Undefined

—

Undefined

—

PG4

—*

PG3

—*

PG0

—*

PG2

—*

PG1

—*

Bit

Initial value :

R/W

Note: * Determined by the state of pins PG4 to PG0.

PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port G pins (PG4 to PG0) must always be performed on PGDR.

Bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read.

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