H8SSLASH2214 datasheet(496/936 Pages) RENESAS

496 / 936 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev.4.00 Sep. 18, 2008 Page 436 of 872

REJ09B0189-0400

(12) Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T

2 state of a TCNT write cycle, and

overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is

not set .

Figure 10.53 shows the operation timing when there is contention between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

H'FFFF

TCNT write data

TCFV flag

Prohibited

Figure 10.53 Contention between TCNT Write and Overflow

(13) Multiplexing of I/O Pins

In the H8S/2214 Group, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the

TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and

the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match

output should not be performed from a multiplexed pin.

(14) Interrupts and Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source, DTC activation source, or DMAC activation source. Interrupts

should therefore be disabled before entering module stop mode.

H8S/2214 Scheda tecnica(PDF) 496 Page - Renesas Technology Corp