H8SSLASH2214 datasheet(500/936 Pages) RENESAS

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Section 11 Watchdog Timer (WDT)

Rev.4.00 Sep. 18, 2008 Page 440 of 872

REJ09B0189-0400

11.2

11.2.1

Timer Counter (TCNT)

R/W

Bit

Initial value :

R/W

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), the OVF flag in TCSR is set to 1.

TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared

to 0. It is not initialized in software standby mode.

Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see

section 11.2.4, Notes on Register Access.

11.2.2

Timer Control/Status Register (TCSR)

OVF

R/(W)*

WT/IT

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value :

R/W

Note: * Only 0 can be written, to clear the flag.

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

TCSR0 is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see

section 11.2.4, Notes on Register Access.

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