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H8S/2214 Scheda tecnica(PDF) 498 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 498 Page - Renesas Technology Corp |
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498 / 936 page ![]() Section 11 Watchdog Timer (WDT) Rev.4.00 Sep. 18, 2008 Page 438 of 872 REJ09B0189-0400 11.1.2 Block Diagram Figure 11.1 shows block diagrams of WDT. Overflow WOVI0 (interrupt request signal) Internal reset signal* TCNT RSTCSR TCSR φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock Clock select Internal clock Bus interface Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by means of a register setting. Either a power-on reset or a manual reset can be selected. Interrupt control Reset control Figure 11.1 Block Diagram of WDT |
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