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H8S/2214 Scheda tecnica(PDF) 532 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 532 Page - Renesas Technology Corp |
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532 / 936 page  Section 12 Serial Communication Interface (SCI) Rev.4.00 Sep. 18, 2008 Page 472 of 872 REJ09B0189-0400 12.2.8 Bit Rate Register (BRR) 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 0 1 R/W 2 1 R/W 1 1 R/W Bit Initial value R/W : : : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 12.3 shows sample BRR settings in asynchronous mode, and table 12.4 shows sample BRR settings in clocked synchronous mode. |
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