H8SSLASH2214 datasheet(530/936 Pages) RENESAS

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Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 470 of 872

REJ09B0189-0400

Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity

addition in asynchronous mode, causing abnormal termination.

Bit 3

PER

Description

[Clearing condition]

(Initial value)*

• When 0 is written to PER after reading PER = 1

[Setting condition]

• When, in reception, the number of 1 bits in the receive data plus the parity bit does

not match the parity setting (even or odd) specified by the O/

E bit in SMR*2

Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of

the transmit character is sent, and transmission has been ended.

The TEND flag is read-only and cannot be modified.

Bit 2

TEND

Description

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR

[Setting conditions]

(Initial value)

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character

Note:

This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not

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