H8SSLASH2214 datasheet(528/936 Pages) RENESAS

528 / 936 page

Section 12 Serial Communication Interface (SCI)

Rev.4.00 Sep. 18, 2008 Page 468 of 872

REJ09B0189-0400

Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from

TDR to TSR and the next serial data can be written to TDR.

Bit 7

TDRE

Description

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR

[Setting conditions]

(Initial value)

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

Note:

This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.

Bit 6

RDRF

Description

[Clearing conditions]

(Initial value)

• When 0 is written to RDRF after reading RDRF = 1

• When the DMAC or DTC* is activated by an RXI interrupt and reads data from

RDR

[Setting condition]

• When serial reception ends normally and receive data is transferred from RSR to

RDR

Note:

RDR and the RDRF flag are not affected and retain their previous values when an error is

detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

This bit is cleared by DTC when DISEL = 0 and furthermore the transfer counter is not

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