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H8S/2214 Scheda tecnica(PDF) 601 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 601 Page - Renesas Technology Corp |
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601 / 936 page ![]() Section 14 RAM Rev.4.00 Sep. 18, 2008 Page 541 of 872 REJ09B0189-0400 14.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to H'FFFFFF in the H8S/2214 Group is directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 14.4 Usage Note DTC register information can be located in addresses H'FFEBC0 to H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0. |
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