H8SSLASH2214 datasheet(605/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 545 of 872

REJ09B0189-0400

15.3

Operation

The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can

be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to

the lower 8 bits. Word data must start at an even address.

The on-chip ROM is enabled and disabled by setting the mode pins (MD2, MD1, and MD0).

These settings are shown in table 15.2.

Table 15.2

Operating Modes and ROM Area

(F-ZTAT Version and Masked ROM Version)

Mode Pin

Operating Mode

FWE

MD2

MD1

MD0

On-Chip ROM

Mode 0

—

Mode 1

Mode 2

Mode 3

Mode 4

Advanced expanded mode with on-chip

ROM disabled

Disabled

Mode 5

Advanced expanded mode with on-chip

ROM disabled

Mode 6

Advanced expanded mode with on-chip

ROM enabled

Enabled (128 kbytes)*

Mode 7

Advanced single-chip mode

Enabled (128 kbytes)*

Mode 8

—

Mode 9

Mode 10

Boot mode (advanced expanded mode

with on-chip ROM enabled)*

Enabled (128 kbytes)*

Mode 11

Boot mode (advanced single-chip

mode)*

Enabled (128 kbytes)*

Mode 12

—

Mode 13

Mode 14

User program mode (advanced expanded

mode with on-chip ROM enabled)*

Enabled (128 kbytes)*

Mode 15

User program mode (advanced single-

chip mode)*

Enabled (128 kbytes)*

Notes:

1. Apart from the fact that flash memory can be erased and programmed, operation is the same as in

advanced expanded mode with on-chip ROM enabled.

2. Apart from the fact that flash memory can be erased and programmed, operation is the same as in

advanced single-chip mode.

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