H8SSLASH2214 datasheet(621/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 561 of 872

REJ09B0189-0400

The flash memory block configuration is shown in table 15.6.

Table 15.6

Flash Memory Erase Blocks

Block (Size)

Addresses

EB0 (1 kbyte)

H'000000 to H'0003FF

EB1 (1 kbyte)

H'000400 to H'0007FF

EB2 (1 kbyte)

H'000800 to H'000BFF

EB3 (1 kbyte)

H'000C00 to H'000FFF

EB4 (28 kbytes)

H'001000 to H'007FFF

EB5 (16 kbytes)

H'008000 to H'00BFFF

EB6 (8 kbytes)

H'00C000 to H'00DFFF

EB7 (8 kbytes)

H'00E000 to H'00FFFF

EB8 (32 kbytes)

H'010000 to H'017FFF

EB9 (32 kbytes)

H'018000 to H'01FFFF

15.7.5

RAM Emulation Register (RAMER)

Bit:

—

RAMS

—

RAM1

RAM0

Initial value:

R/W:

R/W

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER initialized to H'00 by a power-on reset and in

hardware standby mode. It is not initialized by a manual reset and in software standby mode.

RAMER settings should be made in user mode or user program mode.

Flash memory area divisions are shown in table 15.7. To ensure correct operation of the emulation

function, the ROM for which RAM emulation is performed should not be accessed immediately

after this register has been modified. Normal execution of an access immediately after register

modification is not guaranteed.

Bits 7 to 5—Reserved: These bits always read 0.

Bit 4—Reserved: Only 0 may be written to these bits.

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