H8SSLASH2214 datasheet(620/936 Pages) RENESAS

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Section 15 ROM

Rev.4.00 Sep. 18, 2008 Page 560 of 872

REJ09B0189-0400

15.7.3

Erase Block Register 1 (EBR1)

Bit:

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value:

R/W:

R/W

EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is

initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,

when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the

SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be

erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can

be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be

automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and

writes are invalid.

The flash memory block configuration is shown in table 15.6.

15.7.4

Erase Block Register 2 (EBR2)

Bit:

—

EB9

EB8

Initial value:

R/W:

R/W

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,

when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is

not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the

corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1

and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both

EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 2 are reserved and must only be

written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

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