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H8S/2214 Scheda tecnica(PDF) 804 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 804 Page - Renesas Technology Corp |
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804 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 744 of 872 REJ09B0189-0400 B.2 Functions MRA—DTC Mode Register A H'EBC0 to H'EFBF DTC 7 SM1 6 SM0 5 DM1 4 DM0 3 MD1 0 Sz 2 MD0 1 DTS Bit Initial value : : — Unde- fined R/W : — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer 0 1 — 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) DTC Transfer Mode Select DTC Mode Destination Address Mode 1 and 0 Source Address Mode 1 and 0 0 1 Destination side is repeat area or block area Source side is repeat area or block area 0 1 — 0 1 DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by –1 when Sz = 0; by –2 when Sz = 1) 0 1 0 1 0 1 Normal mode Repeat mode Block transfer mode — |
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