H8SSLASH2214 datasheet(805/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 745 of 872

REJ09B0189-0400

MRB—DTC Mode Register B

H'EBC0 to H'EFBF

DTC

CHNE

DISEL

—

Bit

Initial value

R/W

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

DTC Interrupt Select

Reserved

Only 0 should be written to these bits.

After a data transfer ends, the CPU interrupt is disabled unless the

transfer counter is 0 (the DTC clears the interrupt source flag of the

activating interrupt to 0)

After a data transfer ends, the CPU interrupt is enabled (the DTC does

not clear the interrupt source flag of the activating interrupt to 0)

DTC Chain Transfer Enable

End of DTC data transfer (activation waiting state)

DTC chain transfer (new register information is read,

then data is transferred)

SAR—DTC Source Address Register

H'EBC0 to H'EFBF

DTC

43210

Bit

Initial value

—

Unde-

fined

R/W

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Specifies transfer data source address

DAR—DTC Destination Address Register

H'EBC0 to H'EFBF

DTC

43210

Bit

Initial value

—

Unde-

fined

R/W

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Specifies transfer data destination address

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