H8SSLASH2214 datasheet(817/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 757 of 872

REJ09B0189-0400

DTCER—DTC Enable Registers

H'FE16 to H'FE1E

DTC

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

R/W

DTC Activation Enable

DTC activation by this interrupt is disabled

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended

• When the specified number of transfers have ended

DTC activation by this interrupt is enabled

[Holding condition]

• When the DISEL bit is 0 and the specified number of transfers have not ended

DTVECR—DTC Vector Register

H'FE1F

DTC

SWDTE

R/(W)*1

DTVEC6

R/W*2

DTVEC5

R/W*2

DTVEC4

R/W*2

DTVEC3

R/W*2

DTVEC0

R/W*2

DTVEC2

R/W*2

DTVEC1

R/W*2

Notes: 1. Only 1 can be written to the SWDTE bit.

2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.

Bit

Initial value

R/W

DTC Software Activation Enable

Sets vector number for DTC software activation

DTC software activation is disabled

[Clearing conditions]

• When the DISEL bit is 0 and the specified number of transfers have not ended

• When 0 is written to the DISEL bit after a software-activated data transfer end interrupt

(SWDTEND) request has been sent to the CPU

DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended

• When the specified number of transfers have ended

• During data transfer due to software activation

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