H8SSLASH2214 datasheet(814/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 754 of 872

REJ09B0189-0400

SEMR0—Serial Extended Mode Register 0

H'FDF8

SCI0

SSE

R/W

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

ABCS

R/W

ACS0

R/W

ACS2

R/W

ACS1

R/W

Bit

Initial value

R/W

Asynchronous Base Clock Select

SCI0 Select Enable

SCI0 select function disabled

SCI0 select function enabled

When PG1/IRQ7 pin input = 1, TxD0 goes to high-impedance state and SCK0 clock

input is fixed high

SCI0 operates on base clock with frequency of 16 times transfer rate

SCI0 operates on base clock with frequency of 8 times transfer rate

Asynchronous Clock Source Select 2 to 0

External clock input

115.152 kbps average transfer rate

(for

φ = 10.667 MHz only) is selected (SCI0 operates

on base clock with frequency of 16 times transfer rate)

460.606 kbps average transfer rate

(for

φ = 10.667 MHz only) is selected (SCI0 operates on

base clock with frequency of 8 times transfer rate)

Reserved

TPU clock input (AND of TIOCA1 and TIOCA2)

115.196 kbps average transfer rate (for

φ = 16 MHz only)

is selected (SCI0 operates on base clock with frequency

of 16 times transfer rate)

460.784 kbps average transfer rate (for

φ = 16 MHz only)

is selected (SCI0 operates on base clock with frequency

of 16 times transfer rate)

720 kbps average transfer rate (for

φ = 16 MHz only)

is selected (SCI0 operates on base clock with frequency

of 8 times transfer rate)

Reserved Bits

Write 0 to these bits.

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