H8SSLASH2214 datasheet(838/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 778 of 872

REJ09B0189-0400

TCR0—Timer Control Register 0

H'FF10

TPU0

CCLR2

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

R/W

Counter Clear 2 to 0

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel performing

synchronous clearing/synchronous operation *1

TCNT clearing disabled

TCNT cleared by TGRC compare match/input capture *2

TCNT cleared by TGRD compare match/input capture *2

TCNT cleared by counter clearing for another channel performing

synchronous clearing/synchronous operation *1

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit

in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not

cleared because the buffer register setting has priority, and compare

match/input capture does not occur.

Clock Edge 1 and 0

—

Count at rising edge

Count at falling edge

Count at both edges

Time Prescaler 2 to 0

Internal clock: counts on

φ/1

Internal clock: counts on

φ/4

Internal clock: counts on

φ/16

Internal clock: counts on

φ/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

External clock: counts on TCLKC pin input

External clock: counts on TCLKD pin input

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