H8SSLASH2214 datasheet(841/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 781 of 872

REJ09B0189-0400

TIOR0L—Timer I/O Control Register 0L

H'FF13

TPU0

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC0

R/W

IOC2

R/W

IOC1

R/W

Note: 1. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a

buffer register, this setting is invalid and input capture/output compare

is not generated.

Bit

Initial value

R/W

Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer

generated.

I/O Control C3 to C0

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input source

isTIOCC0 pin

Setting prohibited

TGR0C is

output

compare

TGR0C is

input capture

I/O Control D3 to D0

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

Output disabled

Initial output is 0

output

Output disabled

Initial output is 1

output

Capture input source is

TIOCD0 pin

Setting prohibited

TGR0D is

output

compare

TGR0D is

input capture

Note:

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

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