H8SSLASH2214 datasheet(845/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 785 of 872

REJ09B0189-0400

TCR1—Timer Control Register 1

H'FF20

TPU1

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

R/W

Time Prescaler 2 to 0

Internal clock: counts on

φ/1

Internal clock: counts on

φ/4

Internal clock: counts on

φ/16

Internal clock: counts on

φ/64

External clock: counts on TCLKA pin input

External clock: counts on TCLKB pin input

Internal clock: counts on

φ/256

Setting prohibited

Note: This setting is ignored when channel 1 is in phase

counting mode.

Clock Edge 1 and 0

Count at rising edge

Count at falling edge

Count at both edges

Note: The internal clock edge selection is valid when the input

clock is

φ/4 or slower. This setting is ignored if the input

clock is

φ/1, or when overflow/underflow of another

channel is selected. (Counting occurs on the falling edge

φ when φ/1 is selected.)

—

Counter Clear 2 to 0

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*2

0*1

Notes:

Bit 7 is reserved.

It cannot be modified and is always read as 0.

Synchronous operation setting is performed by setting

the SYNC bit in TSYR to 1.

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