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H8S/2214 Scheda tecnica(PDF) 862 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 862 Page - Renesas Technology Corp |
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862 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 802 of 872 REJ09B0189-0400 TCNT0—Timer Counter H'FF74(W) H'FF75(R) WDT0 WDT0 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W Bit Initial value Read/Write RSTCSR—Reset Control/Status Register H'FF76(W) H'FF77(R) WDT0 WDT0 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — Bit Initial value R/W : : : Note: * Only 0 can be written, to clear the flag. RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. Reset Select 0 1 Power-on reset Manual reset Reset Enable 0 1 Note: * The chip is not reset internally, but TCNT and TCSR in WDT0 are reset. No internal reset when TCNT overflows* Internal reset is generated when TCNT overflows Watchdog Overflow Flag 0 1 [Clearing condition] • Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] • When TCNT overflows (from H'FF to H'00) in watchdog timer mode |
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