H8SSLASH2214 datasheet(858/936 Pages) RENESAS

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Appendix B Internal I/O Register

Rev.4.00 Sep. 18, 2008 Page 798 of 872

REJ09B0189-0400

DMACR0A—DMA Control Register 0A

DMACR0B—DMA Control Register 0B

DMACR1A—DMA Control Register 1A

DMACR1B—DMA Control Register 1B

H'FF62

H'FF63

H'FF64

H'FF65

DMAC

DTSZ

R/W

DTID

R/W

RPE

R/W

DTDIR

R/W

DTF3

R/W

DTF0

R/W

DTF2

R/W

DTF1

R/W

Byte size transfer

Word size transfer

Data Transfer Size

MAR incremented after data transfer

(1) When DTSZ=0, MAR + 1 after transfer

(2) When DTSZ=1, MAR + 2 after transfer

MAR decremented after data transfer

(1) When DTSZ=0, MAR – 1 after transfer

(2) When DTSZ=1, MAR – 2 after transfer

Data transfer increment/decrement

Repeat Enable

Data Transfer Direction

Data Tansfer Factor

Channel A

Channel B

Sequential mode transfer (no transfer end interrrupt)

Sequential mode transfer (with transfer end interrupt)

Transfer in repeat mode (no transfer end interrupt)

Transfer in idle mode (with transfer end interrupt)

DTIE

DMABCR

RPE

Transfer from MAR as source address to IOAR as destination address

Transfer from IOAR as source address to MAR as destination address

—

Starts on SCI channel 0 transmit end interrupt

Starts on SCI channel 0 receive end interrupt

Starts on SCI channel 1 transmit end interrupt

Starts on SCI channel 1 receive end interrupt

Starts on TPU channel 0 compare match/input capture A interrupt

Starts on TPU channel 1 compare match/input capture A interrupt

Starts on TPU channel 2 compare match/input capture A interrupt

—

Starts on falling edge of input at DREQ pin*

Starts on LOW level input at DREQ pin

Starts on SCI channel 0 transmit end interrupt

Starts on SCI channel 0 receive end interrupt

Starts on SCI channel 1 transmit end interrupt

Starts on SCI channel 1 receive end interrupt

Starts on TPU channel 0 compare match/input capture A interrupt

Starts on TPU channel 1 compare match/input capture A interrupt

Starts on TPU channel 2 compare match/input capture A interrupt

—

Note: * Detect the first transfer after transfers have been enabled as a LOW level signal.

Bit

DMACR

Initial value

R/W

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