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H8S/2214 Scheda tecnica(PDF) 861 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 861 Page - Renesas Technology Corp |
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861 / 936 page ![]() Appendix B Internal I/O Register Rev.4.00 Sep. 18, 2008 Page 801 of 872 REJ09B0189-0400 TCSR0—Timer Control/Status Register H'FF74(W) H'FF74(R) WDT0 WDT0 7 OVF 0 R/(W)*1 6 WT/ IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 0 CKS0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W Bit Initial value Read/Write Notes: 1. 2. Only 0 can be written, to clear the flag. TCSR is write-protected by a password to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access. If the interval timer interrupt is disabled and the OVF flag is polled, the application should read the OVF = 1 state at least twice. Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 11.2.3, Reset Control/Status Register (RSTCSR). Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 1 TCNT is initialized to H'00 and count operation is halted TCNT counts Timer Mode Select 0 1 Interval timer mode: Interval timer interrupt (WOVI) request is sent to CPU when TCNT overflows Watchdog timer mode: Internal reset can be selected when TCNT overflows* Overflow Flag 0 1 [Clearing condition] • Cleared by reading* 2 TCSR when OVF = 1, then writing 0 to OVF [Setting condition] • When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Clock Select 2 to 0 Clock Overflow Period* (when φ = 10 MHz) φ/2 (Initial value) 51.2 µs φ/64 1.6 ms φ/128 3.2 ms φ/512 13.2 ms φ/2048 52.4 ms φ/8192 209.8 ms φ/32768 838.8 ms φ/131072 3.36 s 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CKS2 CKS1 CKS0 |
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