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H8S/2214 Scheda tecnica(PDF) 134 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 134 Page - Renesas Technology Corp |
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134 / 936 page ![]() Section 3 MCU Operating Modes Rev.4.00 Sep. 18, 2008 Page 74 of 872 REJ09B0189-0400 Bit 2—Manual Reset Select (MRESE): Enables or disables the MRES pin. Table 3.3 shows the relationship between the RES and MRES pin values and type of reset. For details of resets, see section 4.2, Resets. Bit 2 MRESE Description 0 Manual reset is disabled P74/ MRES pin can be used as P74 I/O pin (Initial value) 1 Manual reset is enabled P74/ MRES pin can be used as MRES input pin Table 3.3 Relationship between RES and MRES pin Values and Type of Reset Pins RES MRES Type of Reset 0 * Power-on reset 1 0 Manual reset 1 1 Operating state *: Don’t care Bit 1—Reserved: Read-only bit, always read as 0. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value) Note: When the DTC is used, the RAME bit should not be cleared to 0. |
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