H8SSLASH2214 datasheet(135/936 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.4.00 Sep. 18, 2008 Page 75 of 872

REJ09B0189-0400

3.3

Operating Mode Descriptions

3.3.1

Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a

data bus, and part of port F carries bus control signals.

Pins P13 to P11 function as input ports immediately after a reset. Address (A23 to A21) output

can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)

regardless of the corresponding data direction register (DDR) values. Pin 10 and ports A and B

function as address (A20 to A8) outputs immediately after a reset. Address output can be enabled

or disabled by bits AE3 to AE0 in PFCR regardless of the corresponding DDR values. Pins for

which address output is disabled among pins P13 to P10 and in ports A and B become port outputs

when the corresponding DDR bits are set to 1.

Port C always has an address (A7 to A0) output function.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-

bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

3.3.2

Mode 5