H8SSLASH2214 datasheet(154/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 94 of 872

REJ09B0189-0400

5.2

5.2.1

System Control Register (SYSCR)

—

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

MRESE

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the

detected edge for NMI.

Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control

SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. In a manual

reset, the INTM1, INTM0, NMIEG, and RAME bits are initialized, but the MRESE bit is not.

SYSCR is not initialized in software standby mode.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two

interrupt control modes for the interrupt controller.

Bit 5

Bit 4

Interrupt

INTM1

INTM0

Control Mode

Description

Interrupts are controlled by I bit

(Initial value)

—

Setting prohibited

Interrupts are controlled by bits I2 to I0, and IPR

—

Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.

Bit 3

NMIEG

Description

Interrupt request generated at falling edge of NMI input

(Initial value)

Interrupt request generated at rising edge of NMI input

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