H8SSLASH2214 datasheet(156/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 96 of 872

REJ09B0189-0400

As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range

from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding

interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority

level, level 7, by setting H'7.

When interrupt requests are generated, the highest-priority interrupt according to the priority

levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt

mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if

the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to

the CPU.

5.2.3

IRQ Enable Register (IER)

IRQ7E

R/W

IRQ6E

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ0E

R/W

IRQ2E

R/W

IRQ1E

R/W

Bit

Initial value

R/W

IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests

IRQ7 to IRQ0.

IER is initialized to H'00 by a reset and in hardware standby mode.

It is not initialized in software standby mode.

Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to

IRQ0 are enabled or disabled.

Bit n

IRQnE

Description

IRQn interrupts disabled

(Initial value)

IRQn interrupts enabled

(n = 7 to 0)

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