H8SSLASH2214 datasheet(157/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 97 of 872

REJ09B0189-0400

5.2.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH

IRQ7SCB

R/W

IRQ7SCA

R/W

IRQ6SCB

R/W

IRQ6SCA

R/W

IRQ5SCB

R/W

IRQ4SCA

R/W

IRQ5SCA

R/W

IRQ4SCB

R/W

Bit

Initial value

R/W

ISCRL

IRQ3SCB

R/W

IRQ3SCA

R/W

IRQ2SCB

R/W

IRQ2SCA

R/W

IRQ1SCB

R/W

IRQ0SCA

R/W

IRQ1SCA

R/W

IRQ0SCB

R/W

Bit

Initial value

R/W

The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins

IRQ7 to IRQ0.

The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and

B (IRQ0SCA, IRQ0SCB)

Bits 15 to 0

IRQ7SCB to

IRQ0SCB

IRQ7SCA to

IRQ0SCA

Description

Interrupt request generated at

IRQ7 to IRQ0 input low level

(initial value)

Interrupt request generated at falling edge of

IRQ7 to IRQ0 input

Interrupt request generated at rising edge of

IRQ7 to IRQ0 input

Interrupt request generated at both falling and rising edges of

IRQ7 to IRQ0 input

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