H8SSLASH2214 datasheet(172/936 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 112 of 872

REJ09B0189-0400

5.4.5

Interrupt Response Times

The H8S/2214 Group is capable of fast word transfer instruction to on-chip memory, and the

program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-

speed processing.

Table 5.9 shows interrupt response times—the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5.9 are explained in table 5.10.

Table 5.9

Interrupt Response Times

Normal Mode*

Advanced Mode

No.

Execution Status

INTM1 = 0

INTM1 = 1

INTM1 = 0

INTM1 = 1

Interrupt priority determination*

Number of wait states until executing

instruction ends*

(1 to 19)

+ 2 · S

(1 to 19)

+ 2 · S

(1 to 19)

+ 2 · S

(1 to 19)

+ 2 · S

PC, CCR, EXR stack save

2 · S

3 · S

2 · S

3 · S

Vector fetch

2 · S

Instruction fetch*

2 · S

Internal processing*

Total (using on-chip memory)

11 to 31

12 to 32

13 to 33

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in the H8S/2214 Group.

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