H8SSLASH2214 datasheet(174/936 Pages) RENESAS

Il numero della parte	H8S/2214

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	936 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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174 / 936 page

Section 5 Interrupt Controller

Rev.4.00 Sep. 18, 2008 Page 114 of 872

REJ09B0189-0400

Internal

address bus

Internal

write signal

TGIEA

TGFA

TGIOA

interrupt signal

TIER0 write cycle by CPU

TGIOA exception handling

TIER0 address

Figure 5.8 Contention between Interrupt Generation and Disabling

5.5.2

Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.5.3

Times when Interrupts Are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

H8S/2214 Scheda tecnica(PDF) 174 Page - Renesas Technology Corp