H8SSLASH2214 datasheet(309/936 Pages) RENESAS

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Section 7 DMA Controller

Rev.4.00 Sep. 18, 2008 Page 249 of 872

REJ09B0189-0400

(3) Medium-Speed Mode

When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-

detected.

In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting

modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt

source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is

generated, is less than one state with respect to the DMAC clock (bus master clock), edge

detection may not be possible and the interrupt may be ignored.

Also, in medium-speed mode,

DREQ pin sampling is performed on the rising edge of the medium-

speed clock.

(4) Activation by Falling Edge on

DREQ Pin

DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.

The operation is as follows:

[1] Activation request wait state: Waits for detection of a low level on the

DREQ pin, and

switches to [2].

[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].

[3] Activation request disabled state: Waits for detection of a high level on the

DREQ pin, and

switches to [1].

After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is

enabled is performed by detection of a low level.

(5) Activation Source Acceptance

At the start of activation source acceptance, a low level is detected in both

DREQ pin falling edge

sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is

detected. Therefore, a request is accepted from an internal interrupt or

DREQ pin low level that

occurs before execution of the DMABCRL write to enable transfer.

When the DMAC is activated, take any necessary steps to prevent an internal interrupt or

DREQ

pin low level remaining from the end of the previous transfer, etc.

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