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H8S/2214 Scheda tecnica(PDF) 313 Page - Renesas Technology Corp |
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H8S/2214 Scheda tecnica(HTML) 313 Page - Renesas Technology Corp |
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313 / 936 page ![]() Section 8 Data Transfer Controller (DTC) Rev.4.00 Sep. 18, 2008 Page 253 of 872 REJ09B0189-0400 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.1 DTC Registers Name Abbreviation R/W Initial Value Address* 1 DTC mode register A MRA —* 2 Undefined —* 3 DTC mode register B MRB —* 2 Undefined —* 3 DTC source address register SAR —* 2 Undefined —* 3 DTC destination address register DAR —* 2 Undefined —* 3 DTC transfer count register A CRA —* 2 Undefined —* 3 DTC transfer count register B CRB —* 2 Undefined —* 3 DTC enable registers DTCER R/W H'00 H'FF16 to H'FE1B, H'FE1E DTC vector register DTVECR R/W H'00 H'FE1F Module stop control register A MSTPCRA R/W H'3F H'FDE8 Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot be located in external memory space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. |
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