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H8S/2224 Scheda tecnica(PDF) 494 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 494 Page - Renesas Technology Corp

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Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 5.00 Aug 08, 2006 page 408 of 982
REJ09B0054-0500
TCNT value
TGRB_0
H'0000
TGRC_0
TGRA_0
H'0200
H'0520
TIOCA
H'0200
H'0450
H'0520
H'0450
TGRA_0
H'0450
H'0200
Transfer
Time
Figure 11.16 Example of Buffer Operation (1)
2. When TGR is an input capture register
Figure 11.17 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.



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