H8SSLASH2224 datasheet(531/1071 Pages) RENESAS

531 / 1071 page

Section 12 8-Bit Timers

Rev. 5.00 Aug 08, 2006 page 445 of 982

REJ09B0054-0500

12.3.3

Time Constant Register B (TCORB)

TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (TCORB_2 and

TCORB_3)* comprise a single 16-bit register, so they can be accessed together by word access.

TCORB is continually compared with the value in TCNT. When a match is detected, the

corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is

disabled during the T2 state of a TCORB write cycle.

The timer output from the TMO pin can be freely controlled by the compare-match signal B and

the settings of output select bits OS1 and OS0 in TCSR.

The initial value of TCORB is H'FF.

Note: * Not available in the H8S/2237 Group and H8S/2227 Group.

12.3.4

Timer Control Register (TCR)

TCR selects the TCNT clock source and the time at which TCNT is cleared, and controls interrupt

requests.

Bit

Bit Name

Initial

Value

R/W

Description

CMIEB

R/W

Compare-Match Interrupt Enable B

Selects whether the CMFB interrupt request (CMIB) is

enabled or disabled when the CMFB flag in TCSR is

set to 1.

0: CMFB interrupt request (CMIB) is disabled

1: CMFB interrupt request (CMIB) is enabled

CMIEA

R/W

Compare-Match Interrupt Enable A

Selects whether the CMFA interrupt request (CMIA) is

enabled or disabled when the CMFA flag in TCSR is

set to 1.

0: CMFA interrupt request (CMIA) is disabled

1: CMFA interrupt request (CMIA) is enabled

OVIE

R/W

Timer Overflow Interrupt Enable

Selects whether the OVF interrupt request (OVI) is

enabled or disabled when the OVF flag in TCSR is set

to 1.

0: OVF interrupt request (OVI) is disabled

1: OVF interrupt request (OVI) is enabled

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