H8SSLASH2224 datasheet(528/1071 Pages) RENESAS

528 / 1071 page

Section 12 8-Bit Timers

Rev. 5.00 Aug 08, 2006 page 442 of 982

REJ09B0054-0500

• Module stop mode can be set

At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the

module stop mode.

Note: * Not available in the H8S/2237 Group and H8S/2227 Group.

Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).

External clock

sources

Internal clock*

sources

φ/8

φ/64

φ/8192

Clock 1

Clock 0

Compare-match A1

Compare-match A0

Clear 1

CMIA0

CMIB0

OVI0

CMIA1

CMIB1

OVI1

Interrupt signals

TMO

TMRI01

TCORA_0

Comparator A_0

Comparator B_0

TCORB_0

TCSR_0

TCR_0

TCORA_1

Comparator A_1

TCNT_1

Comparator B_1

TCORB_1

TCSR_1

TCR_1

TMCI01

TCNT_0

Overflow 1

Overflow 0

Compare-match B1

Compare-match B0

TMO1

A/D

conversion

start request

signal

Clock select

Control logic

Clear 0

Legend:

Note: * When a sub-clock is operating in power-down mode,

φ will be f

SUB.

Time constant register A_0

Time constant register B_0

Timer counter _0

Timer control/status register _0

Timer control register _0

TCORA_0:

TCORB_0:

TCNT_0:

TCSR_0:

TCR_0:

Time constant register A_1

Time constant register B_1

Timer counter _1

Timer control/status register _1

Timer control register _1

TCORA_1:

TCORB_1:

TCNT_1:

TCSR_1:

TCR_1:

Figure 12.1 Block Diagram of 8-Bit Timer Module

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