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H8S/2224 Scheda tecnica(PDF) 540 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 540 Page - Renesas Technology Corp |
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540 / 1071 page ![]() Section 12 8-Bit Timers Rev. 5.00 Aug 08, 2006 page 454 of 982 REJ09B0054-0500 φ External clock input pin TCNT input clock TCNT N − 1 N N + 1 Figure 12.4 Count Timing for External Clock Input 12.5.2 Timing of CMFA and CMFB Setting when a Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 12.5 shows the timing of CMF flag setting. φ TCNT NN + 1 TCOR N Compare-match signal CMF Figure 12.5 Timing of CMF Setting |
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