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H8S/2224 Scheda tecnica(PDF) 541 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 541 Page - Renesas Technology Corp |
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541 / 1071 page ![]() Section 12 8-Bit Timers Rev. 5.00 Aug 08, 2006 page 455 of 982 REJ09B0054-0500 12.5.3 Timing of Timer Output when a Compare-Match Occurs When a compare-match occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Figure 12.6 shows the timing when the output is set to toggle at compare- match A. φ Compare-match A signal Timer output pin Figure 12.6 Timing of Timer Output 12.5.4 Timing of Compare-Match Clear when a Compare-Match Occurs TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.7 shows the timing of this operation. φ N H'00 Compare-match signal TCNT Figure 12.7 Timing of Compare-Match Clear |
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