H8SSLASH2224 datasheet(543/1071 Pages) RENESAS

543 / 1071 page

Section 12 8-Bit Timers

Rev. 5.00 Aug 08, 2006 page 457 of 982

REJ09B0054-0500

12.6

Operation with Cascaded Connection

If bits CKS2 to CKS0 in one of TCR_0 and TCR_1 (TCR_2 and TCR_3)* are set to B'100, the 8-

bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer can be

used (16-bit timer mode) or compare-matches of 8-bit channel 0 (channel 2)* can be counted by

the timer of channel 1 (channel 3)* (compare-match count mode). In the case that channel 0 is

connected to channel 1 in cascade, the timer operates as described below.

Note: * Not available in the H8S/2237 Group and H8S/2227 Group.

12.6.1

16-Bit Count Mode

When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer

with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.

• Setting of compare-match flags

 The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.

 The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.

• Counter clear specification

 If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match,

the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-

match occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is cleared even if

counter clear by the TMRI01 pin has also been set.

 The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot

be cleared independently.

• Pin output

 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with

the 16-bit compare-match conditions.

 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with

the lower 8-bit compare-match conditions.

12.6.2

Compare-Match Count Mode

When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare-match A for channel 0.

Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,

generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the

settings for each channel.

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