H8SSLASH2224 datasheet(587/1071 Pages) RENESAS

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 501 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3



All 0



Reserved

The read value is undefined. In order to avoid malfunction,

do not use bit manipulation instructions. These bits cannot

be modified.

CMD2

CMD1

CMD0

Command Bits

These bits issue a command to control IEB

communications. When the CMX flag in IEFLG is set after

the command issuance, the command is indicated to be in

execution. When the CMX flag becomes 0, the operation

state is entered. These bits are read as 0. The read value

is undefined. Do not use a bit manipulation instruction that

causes malfunction.

000: No operation. Operation is not affected.

001: Unlock (required from other units)*

010: Requires communications as the master

011: Stops master communications*

100: Undefined bits. Operation is not affected by this

command.

101: Requires data transfer from the slave.

110: Stops data transfer from the slave*

111: Undefined bits. Operation is not affected by this

command.

Notes: 1. Do not execute this command in slave communications. Execute this command after

slave communications ends or in master communications. If this command is issued in

slave communications, this command is ignored.

2. This command is valid during master communications (MRQ = 1). In other states, this

command issuance is ignored. If this command is issued in master communications, the

communications controller immediately enters the wait state. At this time, the issued

master transmission request ends (MRQ = 0).

3. This command is valid during slave communications (SRQ = 1). In other states, this

command issuance is ignored. Once this command was issued in slave transmission,

the SRQ flag is 0 before slave transmission. Therefore, a transmit request from the

master is not responded. If a transmit request is issued during slave transmission, the

transmission stops and the wait state is entered (SRQ = 0).

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