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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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H8S/2224 Scheda tecnica(PDF) 586 Page - Renesas Technology Corp |
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H8S/2224 Scheda tecnica(HTML) 586 Page - Renesas Technology Corp |
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586 / 1071 page  Section 14 IEBus™ Controller (IEB) [H8S/2258 Group] Rev. 5.00 Aug 08, 2006 page 500 of 982 REJ09B0054-0500 Bit Bit Name Initial Value R/W Description 2 LUEE 0 R/W Last Byte Underrun Enable Sets whether to generate an underrun error when the last data field byte is transferred in data transmission. If the IEB reads from IETBR when the TxRDY flag is set (the transmit buffer register (IETBR) is empty), an underrun error occurs. In transmission using the DTC, an underrun error occurs at the last byte transmission if the CPU did not clear the TxRDY flag, because the DTC does not clear the TxRDY flag. When the DTC is used, set this bit to 0 to mask an underrun error generated at the last byte transmission. When the DTC is not used, set this bit to 1 to generate an underrun error at the last byte transmission. 0: An underrun error does not occur at the last byte transmission (when using the DTC) 1: An underrun error does not occur at the last byte transmission (when not using the DTC) 1, 0 All 0 Reserved This bit is always read as 0 and cannot be modified. 14.3.2 IEBus Command Register (IECMR) IECMR issues commands to control IEB communications. Since this register is a write-only register, bit-manipulation instructions should not be used when writing. See section 2.9.4, Access Methods for Registers with Write-Only Bits. |
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