H8SSLASH2224 datasheet(585/1071 Pages) RENESAS

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Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]

Rev. 5.00 Aug 08, 2006 page 499 of 982

REJ09B0054-0500

Bit

Bit Name

Initial

Value

R/W

Description

DEE

R/W

Broadcast Receive Error Interrupt Enable

Since the acknowledgement is not returned between the

master and slave units in broadcast reception, the master

unit cannot decide whether the slave unit is in the receive

enabled state. If this bit is set to 1, a reception error

interrupt occurs (note that there is not the corresponding bit

in the IEBus receive error flag register to this error) when

the receive buffer is not in the receive enabled state during

receiving the control field in broadcast reception (when the

RE bit is not set to 1 or the RxRDY flag is set.). At this time,

the master address is stored in IEMA1 and IEMA2. The

receive data is not stored in the IERCTL.

While this bit is 0, a reception error interrupt does not occur

when the receive buffer is not in the receive enabled state,

and the reception stops and enters the wait state. The

master address is not saved.

0: A broadcast receive error is not generated up to the

control field.

1: A broadcast receive error is generated up to the control

field.

CKS

R/W

Input Clock Select

Always set this bit to 0 in this LSI. Selects clock used by

the IEB.

R/W

Receive Enable

Enables/disables IEB reception. This bit must be set at the

initial setting before frame reception. Changing this bit

before receiving the control field is valid, however,

changing this bit after receiving the control field is invalid

and the value before the change is validated.

0: Reception is disabled.

1: Reception is enabled.

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