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H8S/2224 Scheda tecnica(PDF) 684 Page - Renesas Technology Corp

Il numero della parte H8S/2224
Spiegazioni elettronici  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  1071 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S/2224 Scheda tecnica(HTML) 684 Page - Renesas Technology Corp

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Section 15 Serial Communication Interface (SCI)
Rev. 5.00 Aug 08, 2006 page 598 of 982
REJ09B0054-0500
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR
[2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DMAC*
1 or the DTC*2 is
activated by a transmit-data-
empty interrupt (TXI) request,
and data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DR to
0, clear DDR to 1, then clear the
TE bit in SCR to 0.
Notes: 1. Supported only by the H8S/2239
Group.
2. The case, in which the DTC
automatically clears the TDRE
flag, occurs only when DISEL in
DTC is 0 with the transfer
counter not being 0. Therefore,
the TDRE flag should be cleared
by CPU when DISEL is 1, or
when DISEL is 0 with the
transfer counter being 0.
Figure 15.14 Sample Multiprocessor Serial Transmission Flowchart



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