H8SSLASH2224 datasheet(688/1071 Pages) RENESAS

688 / 1071 page

Section 15 Serial Communication Interface (SCI)

Rev. 5.00 Aug 08, 2006 page 602 of 982

REJ09B0054-0500

15.6

Operation in Clocked Synchronous Mode

Figure 15.17 shows the general format for clocked synchronous communication. In clocked

synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked

synchronous serial communication, data on the transmission line is output from one falling edge of

the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous

with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the

MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI,

the transmitter and receiver are independent units, enabling full-duplex communication through

the use of a common clock. Both the transmitter and the receiver also have a double-buffered

structure, so data can be read or written during transmission or reception, enabling continuous data

transfer.

Don't care

One unit of transfer data (character or frame)

Bit 0

Serial data

Synchronization

clock

Bit 1

Bit 3

Bit 4

Bit 5

LSB

MSB

Bit 2

Bit 6

Bit 7

Note: * High except in continuous transfer

Figure 15.17 Data Format in Synchronous Communication (For LSB-First)

15.6.1

Clock

Either an internal clock generated by the on-chip baud rate generator or an external

synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and

CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from

the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no

transfer is performed the clock is fixed high.

15.6.2

SCI Initialization (Clocked Synchronous Mode)

Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the

SCI should be initialized as described in a sample flowchart in figure 15.18. When the operating

mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before

making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag

is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,

FER, and ORER flags, or the contents of RDR.

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