H8SSLASH2224 datasheet(719/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 633 of 982

REJ09B0054-0500

Section 16 I2C Bus Interface (IIC) (Option)

An I2C bus interface is available as an option. Observe the following notes when using this option.

1. For masked ROM versions, a W is added to the part number in products in which this optional

function is used.

Examples: HD6432239WTE

The H8S/2258 Group, H8S/2239 Group, and H8S/2238 Group have an internal I2C bus

interface of two channels.

The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus)

interface functions. The register configuration that controls the I2C bus differs partly from the

Philips configuration, however.

The I2C bus interface data transfer is performed using a data line (SDA) and a clock line (SCL) for

each channel, which allows efficient use of connectors and the area of the PCB.

Notes: 1. An I2C bus interface is not available in the H8S/2237 Group and H8S/2227 Group.

2. When the power supply voltage ranges from 2.2 V to 2.7 V, the I2C bus interface is not

available.

16.1

Features

• Selection of I2C bus format or clocked synchronous serial format

 I2C bus format: addressing format with acknowledge bit, for master/slave operation

 Clocked synchronous serial format: non-addressing format without acknowledge bit, for

master operation only

I2C bus format

• Two ways of setting slave address

• Start and stop conditions generated automatically in master mode

• Selection of acknowledge output levels when receiving

• Automatic loading of acknowledge bit when transmitting

• Wait function in master mode

A wait can be inserted by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait can be cleared by clearing the interrupt flag.

IFIIC05C_000020020700

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