H8SSLASH2224 datasheet(720/1071 Pages) RENESAS

720 / 1071 page

Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 634 of 982

REJ09B0054-0500

• Wait function in slave mode

A wait request can be generated by driving the SCL pin low after data transfer, excluding

acknowledgement. The wait request is cleared when the next transfer becomes possible.

• Interrupt sources

 Data transfer end (including transmission mode transition with I2C bus format and address

reception after loss of master arbitration)

 Address match: when any slave address matches or the general call address is received in

slave receive mode

 Start condition detection (in master mode)

 Stop condition detection (in slave mode)

• Selection of 16 internal clocks (in master mode)

• Direct bus drive

 Two pins, P35/SCL0 and P34/SDA0, function as NMOS open-drain outputs when the bus

drive function is selected.

 Two pins, P33/SCL1 and P32/SDA1, function as NMOS-only outputs when the bus drive

function is selected.

Figure 16.1 shows a block diagram of the I2C bus interface. Figure 16.2 shows an example of I/O

pin connections to external circuits. Channel I/O pins are NMOS open drains, and it is possible to

apply voltages in excess of the power supply (Vcc) voltage for this LSI. Set the upper limit of

voltage applied to the power supply (Vcc) power supply range +0.3 V. Channel 1 I/O pins are

driven solely by NMOS, so in terms of appearance they carry out the same operations as an

NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the

voltage of the power supply (Vcc) of this LSI.

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