H8SSLASH2224 datasheet(723/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 637 of 982

REJ09B0054-0500

ICE is 1. For details on the module stop control register, refer to section 24.1.2, Module Stop

Control Registers A to C (MSTPCRA to MSTPCRC).

• I2C bus data register_0 (ICDR_0)*

• Slave address register_0 (SAR_0)*

• Second slave address register_0 (SARX_0)*

• I2C bus mode register_0 (ICMR_0)*

• I2C bus control register_0 (ICCR_0)*

• I2C bus status register_0 (ICSR_0)*

• I2C bus data register_1 (ICDR_1)*

• Slave address register_1 (SAR_1)*

• Second slave address register_1 (SARX_1)*

• I2C bus mode register_1 (ICMR_1)*

• I2C bus control register_1 (ICCR_1)*

• I2C bus status register_1 (ICSR_1)*

• DDC switch register (DDCSWR)

• Serial control register X (SCRX)

Note: * Some of the registers in the I2C bus interface are allocated to the same addresses of

other registers. The IICE bit in serial control register X (SCRX) selects each register.

16.3.1 I2C Bus Data Register (ICDR)

ICDR is an 8-bit readable/writable register that is used as a transmit data register when

transmitting and a receive data register when receiving. ICDR is divided internally into a shift

three registers are performed automatically in coordination with changes in the bus state, and

affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit

buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When

RDRF is 1, it shows that the valid receive data is stored in the receive buffer.

If I2C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following

transmission/reception of one frame of data using ICDRS, data is transferred automatically from

ICDRT to ICDRS. If I2C is in receive mode and no previous data remains in ICDRR (the RDRF

flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred

automatically from ICDRS to ICDRR.

If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and

receive data are stored differently. Transmit data should be written justified toward the MSB side

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