H8SSLASH2224 datasheet(726/1071 Pages) RENESAS

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 640 of 982

REJ09B0054-0500

Table 16.2 Transfer Format

SAR

SARX

FSX

2C Transfer Format

SAR and SARX are used as the slave addresses with the I

2C bus

format.

Only SAR is used as the slave address with the I

2C bus format.

Only SARX is used as the slave address with the I

2C bus format.

Clock synchronous serial format (SAR and SARX are invalid)

16.3.4 I2C Bus Mode Register (ICMR)

ICMR sets the transfer format and transfer rate. It can only be accessed when the ICE bit in ICCR

is 1.

Bit

Bit Name

Initial

Value

R/W

Description

MLS

R/W

MSB-First/LSB-First Select

0: MSB-first

1: LSB-first

Set this bit to 0 when the I

2C bus format is used.

WAIT

R/W

Wait Insertion Bit

This bit is valid only in master mode with the I

2C bus

format.

When WAIT is set to 1, after the fall of the clock for the final

data bit, the IRIC flag is set to 1 in ICCR, and a wait state

begins (with SCL at the low level). When the IRIC flag is

cleared to 0 in ICCR, the wait ends and the acknowledge

bit is transferred.

If WAIT is cleared to 0, data and acknowledge bits are

transferred consecutively with no wait inserted.

The IRIC flag in ICCR is set to 1 on completion of the

acknowledge bit transfer, regardless of the WAIT setting.

CKS2

CKS1

CKS0

R/W

Serial Clock Select 2 to 0

This bit is valid only in master mode.

These bits select the required transfer rate, together with

the IICX 1 and IICX0 bit in SCRX. Refer to table 16.3.

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