H8SSLASH2224 datasheet(757/1071 Pages) RENESAS

Il numero della parte	H8S/2224

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	1071 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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Section 16 I

2C Bus Interface (IIC) (Option)

Rev. 5.00 Aug 08, 2006 page 671 of 982

REJ09B0054-0500

8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.

9. Dummy-read ICDR to release SCL on the slave side.

10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL

is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. At the

same time, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.

SDA

(master output)

SDA

(slave output)

Bit 7

Bit 6

Bit 5

Bit 7

Bit 6

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ICDRT

ICDRS

IRIC

TDRE

SCL

(master output)

SCL

(slave output)

Slave receive mode

Slave transmit mode

[3] ICDR write

User processing

Data 1

Data 2

Data 1

Data 2

[3] IRIC clearance

[5] IRIC clearance

[5] ICDR write

[2]

[4]

Figure 16.18 Example of Slave Transmit Mode Operation Timing (MLS = 0)

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